Name gthe3_channel_simmodel.txt gthe3_channel_wiz_wrapper.txt gthe3_channel_wiz_wrapped.txt gthe4_channel_simmodel.txt gthe4_channel_wiz_wrapper.txt gthe4_channel_wiz_wrapped.txt gthe4_channel_wiz_jesd_wrapped.txt
ACJTAG_DEBUG_MODE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
ACJTAG_MODE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
ACJTAG_RESET 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
ADAPT_CFG0 16'hF800 16'hF800 16'b1111100000000000 16'h9200 16'h9200 16'b0001000000000000 16'b0001000000000000
ADAPT_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h801C 16'h801C 16'b1100100000000000 16'b1100100000000000
ADAPT_CFG2 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ALIGN_COMMA_DOUBLE "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
ALIGN_COMMA_ENABLE 10'b0001111111 10'b0001111111 10'b0000000000 10'b0001111111 10'b0001111111 10'b0000000000 10'b0000000000
ALIGN_COMMA_WORD 1 1 1 1 1 1 1
ALIGN_MCOMMA_DET "TRUE" "TRUE" "FALSE" "TRUE" "TRUE" "FALSE" "FALSE"
ALIGN_MCOMMA_VALUE 10'b1010000011 10'b1010000011 10'b1010000011 10'b1010000011 10'b1010000011 10'b1010000011 10'b1010000011
ALIGN_PCOMMA_DET "TRUE" "TRUE" "FALSE" "TRUE" "TRUE" "FALSE" "FALSE"
ALIGN_PCOMMA_VALUE 10'b0101111100 10'b0101111100 10'b0101111100 10'b0101111100 10'b0101111100 10'b0101111100 10'b0101111100
A_RXOSCALRESET 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
A_RXPROGDIVRESET 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
A_RXTERMINATION 1'b1 1'b1 1'b1 1'b1
A_TXDIFFCTRL 5'b01100 5'b01100 5'b01100 5'b01100
A_TXPROGDIVRESET 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
CAPBYPASS_FORCE 1'b0 1'b0 1'b0 1'b0
CBCC_DATA_SOURCE_SEL "DECODED" "DECODED" "ENCODED" "DECODED" "DECODED" "ENCODED" "ENCODED"
CDR_SWAP_MODE_EN 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
CFOK_PWRSVE_EN 1'b1 1'b1 1'b1 1'b1
CHAN_BOND_KEEP_ALIGN "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
CHAN_BOND_MAX_SKEW 7 7 1 7 7 1 1
CHAN_BOND_SEQ_1_1 10'b0101111100 10'b0101111100 10'b0000000000 10'b0101111100 10'b0101111100 10'b0000000000 10'b0000000000
CHAN_BOND_SEQ_1_2 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000
CHAN_BOND_SEQ_1_3 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000
CHAN_BOND_SEQ_1_4 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000
CHAN_BOND_SEQ_1_ENABLE 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111
CHAN_BOND_SEQ_2_1 10'b0100000000 10'b0100000000 10'b0000000000 10'b0100000000 10'b0100000000 10'b0000000000 10'b0000000000
CHAN_BOND_SEQ_2_2 10'b0100000000 10'b0100000000 10'b0000000000 10'b0100000000 10'b0100000000 10'b0000000000 10'b0000000000
CHAN_BOND_SEQ_2_3 10'b0100000000 10'b0100000000 10'b0000000000 10'b0100000000 10'b0100000000 10'b0000000000 10'b0000000000
CHAN_BOND_SEQ_2_4 10'b0100000000 10'b0100000000 10'b0000000000 10'b0100000000 10'b0100000000 10'b0000000000 10'b0000000000
CHAN_BOND_SEQ_2_ENABLE 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111
CHAN_BOND_SEQ_2_USE "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
CHAN_BOND_SEQ_LEN 2 2 1 2 2 1 1
CH_HSPMUX 16'h2424 16'h2424 16'b0010010000100100 16'b0010010000100100
CKCAL1_CFG_0 16'b0000000000000000 16'b0000000000000000 16'b1100000011000000 16'b1100000011000000
CKCAL1_CFG_1 16'b0000000000000000 16'b0000000000000000 16'b0101000011000000 16'b0101000011000000
CKCAL1_CFG_2 16'b0000000000000000 16'b0000000000000000 16'b0000000000001010 16'b0000000000001010
CKCAL1_CFG_3 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000
CKCAL2_CFG_0 16'b0000000000000000 16'b0000000000000000 16'b1100000011000000 16'b1100000011000000
CKCAL2_CFG_1 16'b0000000000000000 16'b0000000000000000 16'b1000000011000000 16'b1000000011000000
CKCAL2_CFG_2 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000
CKCAL2_CFG_3 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000
CKCAL2_CFG_4 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000
CKCAL_RSVD0 16'h4000 16'h4000 16'b0000000010000000 16'b0000000010000000
CKCAL_RSVD1 16'h0000 16'h0000 16'b0000010000000000 16'b0000010000000000
CLK_CORRECT_USE "TRUE" "TRUE" "FALSE" "TRUE" "TRUE" "FALSE" "FALSE"
CLK_COR_KEEP_IDLE "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
CLK_COR_MAX_LAT 20 20 12 20 20 12 12
CLK_COR_MIN_LAT 18 18 8 18 18 8 8
CLK_COR_PRECEDENCE "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
CLK_COR_REPEAT_WAIT 0 0 0 0 0 0 0
CLK_COR_SEQ_1_1 10'b0100011100 10'b0100011100 10'b0000000000 10'b0100011100 10'b0100011100 10'b0000000000 10'b0000000000
CLK_COR_SEQ_1_2 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000
CLK_COR_SEQ_1_3 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000
CLK_COR_SEQ_1_4 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000 10'b0000000000
CLK_COR_SEQ_1_ENABLE 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111
CLK_COR_SEQ_2_1 10'b0100000000 10'b0100000000 10'b0000000000 10'b0100000000 10'b0100000000 10'b0000000000 10'b0000000000
CLK_COR_SEQ_2_2 10'b0100000000 10'b0100000000 10'b0000000000 10'b0100000000 10'b0100000000 10'b0000000000 10'b0000000000
CLK_COR_SEQ_2_3 10'b0100000000 10'b0100000000 10'b0000000000 10'b0100000000 10'b0100000000 10'b0000000000 10'b0000000000
CLK_COR_SEQ_2_4 10'b0100000000 10'b0100000000 10'b0000000000 10'b0100000000 10'b0100000000 10'b0000000000 10'b0000000000
CLK_COR_SEQ_2_ENABLE 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111
CLK_COR_SEQ_2_USE "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
CLK_COR_SEQ_LEN 2 2 1 2 2 1 1
CPLL_CFG0 16'h20F8 16'h20F8 16'b0110011111111000 16'h01FA 16'h01FA 16'b0000000111111010 16'b0000000111111010
CPLL_CFG1 16'hA494 16'hA494 16'b1010010010101100 16'h24A9 16'h24A9 16'b0000000000100011 16'b0000000000100011
CPLL_CFG2 16'hF001 16'hF001 16'b0101000000000111 16'h6807 16'h6807 16'b0000000000000010 16'b0000000000000010
CPLL_CFG3 6'h00 6'h00 6'b000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
CPLL_FBDIV 4 4 2 4 4 2 2
CPLL_FBDIV_45 4 4 5 4 4 5 5
CPLL_INIT_CFG0 16'h001E 16'h001E 16'b0000001010110010 16'h001E 16'h001E 16'b0000001010110010 16'b0000001010110010
CPLL_INIT_CFG1 8'h00 8'h00 8'b00000000
CPLL_LOCK_CFG 16'h01E8 16'h01E8 16'b0000000111101000 16'h01E8 16'h01E8 16'b0000000111101000 16'b0000000111101000
CPLL_REFCLK_DIV 1 1 1 1 1 1 1
CTLE3_OCAP_EXT_CTRL 3'b000 3'b000 3'b000 3'b000
CTLE3_OCAP_EXT_EN 1'b0 1'b0 1'b0 1'b0
DDI_CTRL 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00
DDI_REALIGN_WAIT 15 15 15 15 15 15 15
DEC_MCOMMA_DETECT "TRUE" "TRUE" "FALSE" "TRUE" "TRUE" "FALSE" "FALSE"
DEC_PCOMMA_DETECT "TRUE" "TRUE" "FALSE" "TRUE" "TRUE" "FALSE" "FALSE"
DEC_VALID_COMMA_ONLY "TRUE" "TRUE" "FALSE" "TRUE" "TRUE" "FALSE" "FALSE"
DELAY_ELEC 1'b0 1'b0 1'b0 1'b0
DFE_D_X_REL_POS 1'b0 1'b0 1'b0
DFE_VCM_COMP_EN 1'b0 1'b0 1'b0
DMONITOR_CFG0 10'h000 10'h000 10'b0000000000 10'h000 10'h000 10'b0000000000 10'b0000000000
DMONITOR_CFG1 8'h00 8'h00 8'b00000000 8'h00 8'h00 8'b00000000 8'b00000000
ES_CLK_PHASE_SEL 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
ES_CONTROL 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000
ES_ERRDET_EN "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
ES_EYE_SCAN_EN "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
ES_HORZ_OFFSET 12'h000 12'h000 12'b000000000000 12'h800 12'h800 12'b000000000000 12'b000000000000
ES_PMA_CFG 10'b0000000000 10'b0000000000 10'b0000000000
ES_PRESCALE 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000
ES_QUALIFIER0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER1 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER2 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER3 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER4 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER5 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER6 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER7 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER8 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUALIFIER9 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK1 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK2 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK3 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK4 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK5 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK6 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK7 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK8 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_QUAL_MASK9 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK1 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK2 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK3 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK4 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK5 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK6 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK7 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK8 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
ES_SDATA_MASK9 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
EVODD_PHI_CFG 11'b00000000000 11'b00000000000 11'b00000000000
EYE_SCAN_SWAP_EN 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
FTS_DESKEW_SEQ_ENABLE 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111
FTS_LANE_DESKEW_CFG 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111 4'b1111
FTS_LANE_DESKEW_EN "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
GEARBOX_MODE 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000
GM_BIAS_SELECT 1'b0 1'b0 1'b0
ISCAN_CK_PH_SEL2 1'b0 1'b0 1'b0 1'b0
LOCAL_MASTER 1'b0 1'b0 1'b1 1'b0 1'b0 1'b1 1'b1
LPBK_BIAS_CTRL 3'b000 3'b000 3'b100 3'b100
LPBK_EN_RCAL_B 1'b0 1'b0 1'b0 1'b0
LPBK_EXT_RCAL 4'b0000 4'b0000 4'b1000 4'b1000
LPBK_IND_CTRL0 3'b000 3'b000 3'b000 3'b000
LPBK_IND_CTRL1 3'b000 3'b000 3'b000 3'b000
LPBK_IND_CTRL2 3'b000 3'b000 3'b000 3'b000
LPBK_RG_CTRL 4'b0000 4'b0000 4'b1110 4'b1110
OOBDIVCTL 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00
OOB_PWRUP 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
PCI3_AUTO_REALIGN "FRST_SMPL" "FRST_SMPL" "OVR_1K_BLK" "FRST_SMPL" "FRST_SMPL" "OVR_1K_BLK" "OVR_1K_BLK"
PCI3_PIPE_RX_ELECIDLE 1'b1 1'b1 1'b0 1'b1 1'b1 1'b0 1'b0
PCI3_RX_ASYNC_EBUF_BYPASS 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00
PCI3_RX_ELECIDLE_EI2_ENABLE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
PCI3_RX_ELECIDLE_H2L_COUNT 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000
PCI3_RX_ELECIDLE_H2L_DISABLE 3'b000 3'b000 3'b000 3'b000 3'b000 3'b000 3'b000
PCI3_RX_ELECIDLE_HI_COUNT 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000
PCI3_RX_ELECIDLE_LP4_DISABLE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
PCI3_RX_FIFO_DISABLE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
PCIE3_CLK_COR_EMPTY_THRSH 5'b00000 5'b00000 5'b00000 5'b00000
PCIE3_CLK_COR_FULL_THRSH 6'b010000 6'b010000 6'b010000 6'b010000
PCIE3_CLK_COR_MAX_LAT 5'b01000 5'b01000 5'b00100 5'b00100
PCIE3_CLK_COR_MIN_LAT 5'b00100 5'b00100 5'b00000 5'b00000
PCIE3_CLK_COR_THRSH_TIMER 6'b001000 6'b001000 6'b001000 6'b001000
PCIE_BUFG_DIV_CTRL 16'h0000 16'h0000 16'b0001000000000000 16'h0000 16'h0000 16'b0011010100000000 16'b0011010100000000
PCIE_PLL_SEL_MODE_GEN12 2'h0 2'h0 2'b10 2'b10
PCIE_PLL_SEL_MODE_GEN3 2'h0 2'h0 2'b10 2'b10
PCIE_PLL_SEL_MODE_GEN4 2'h0 2'h0 2'b10 2'b10
PCIE_RXPCS_CFG_GEN3 16'h0000 16'h0000 16'b0000001010100100 16'h0000 16'h0000 16'b0000101010100101 16'b0000101010100101
PCIE_RXPMA_CFG 16'h0000 16'h0000 16'b0000000000001010 16'h0000 16'h0000 16'b0010100000001010 16'b0010100000001010
PCIE_TXPCS_CFG_GEN3 16'h0000 16'h0000 16'b0010010010100100 16'h0000 16'h0000 16'b0010010010100100 16'b0010010010100100
PCIE_TXPMA_CFG 16'h0000 16'h0000 16'b0000000000001010 16'h0000 16'h0000 16'b0010100000001010 16'b0010100000001010
PCS_PCIE_EN "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
PCS_RSVD0 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000 16'b0000000000000000
PCS_RSVD1 3'b000 3'b000 3'b000
PD_TRANS_TIME_FROM_P2 12'h03C 12'h03C 12'b000000111100 12'h03C 12'h03C 12'b000000111100 12'b000000111100
PD_TRANS_TIME_NONE_P2 8'h19 8'h19 8'b00011001 8'h19 8'h19 8'b00011001 8'b00011001
PD_TRANS_TIME_TO_P2 8'h64 8'h64 8'b01100100 8'h64 8'h64 8'b01100100 8'b01100100
PLL_SEL_MODE_GEN12 2'h0 2'h0 2'b11
PLL_SEL_MODE_GEN3 2'h0 2'h0 2'b11
PMA_RSV1 16'h0000 16'h0000 16'b1111000000000000
PREIQ_FREQ_BST 0 0 0 0
PROCESS_PAR 3'b010 3'b010 3'b010 3'b010 3'b010 3'b010 3'b010
RATE_SW_USE_DRP 1'b0 1'b0 1'b1 1'b0 1'b0 1'b1 1'b1
RCLK_SIPO_DLY_ENB 1'b0 1'b0 1'b0 1'b0
RCLK_SIPO_INV_EN 1'b0 1'b0 1'b0 1'b0
RESET_POWERSAVE_DISABLE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RTX_BUF_CML_CTRL 3'b010 3'b010 3'b010 3'b010
RTX_BUF_TERM_CTRL 2'b00 2'b00 2'b00 2'b00
RXBUFRESET_TIME 5'b00001 5'b00001 5'b00011 5'b00001 5'b00001 5'b00011 5'b00011
RXBUF_ADDR_MODE "FULL" "FULL" "FAST" "FULL" "FULL" "FAST" "FAST"
RXBUF_EIDLE_HI_CNT 4'b1000 4'b1000 4'b1000 4'b1000 4'b1000 4'b1000 4'b1000
RXBUF_EIDLE_LO_CNT 4'b0000 4'b0000 4'b0000 4'b0000 4'b0000 4'b0000 4'b0000
RXBUF_EN "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
RXBUF_RESET_ON_CB_CHANGE "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
RXBUF_RESET_ON_COMMAALIGN "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
RXBUF_RESET_ON_EIDLE "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
RXBUF_RESET_ON_RATE_CHANGE "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
RXBUF_THRESH_OVFLW 0 0 57 0 0 57 57
RXBUF_THRESH_OVRD "FALSE" "FALSE" "TRUE" "FALSE" "FALSE" "TRUE" "TRUE"
RXBUF_THRESH_UNDFLW 4 4 3 4 4 3 3
RXCDRFREQRESET_TIME 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001
RXCDRPHRESET_TIME 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001
RXCDR_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0003 16'h0003 16'b0000000000000011 16'b0000000000000011
RXCDR_CFG0_GEN3 16'h0000 16'h0000 16'b0000000000000000 16'h0003 16'h0000 16'b0000000000000011 16'b0000000000000011
RXCDR_CFG1 16'h0080 16'h0080 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXCDR_CFG1_GEN3 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXCDR_CFG2 16'h07E6 16'h07E6 16'b0000011111100110 16'h0164 16'h0155 16'b0000001001101001 16'b0000001001101001
RXCDR_CFG2_GEN2 10'h164 10'h164 10'b1001101001 10'b1001101001
RXCDR_CFG2_GEN3 16'h0000 16'h0000 16'b0000011111100110 16'h0034 16'h0000 16'b0000001001101001 16'b0000001001101001
RXCDR_CFG2_GEN4 16'h0034 16'h0000 16'b0000000101100100 16'b0000000101100100
RXCDR_CFG3 16'h0000 16'h0000 16'b0000000000000000 16'h0024 16'h002A 16'b0000000000010000 16'b0000000000010000
RXCDR_CFG3_GEN2 6'h24 6'h24 6'b010000 6'b010000
RXCDR_CFG3_GEN3 16'h0000 16'h0000 16'b0000000000000000 16'h0024 16'h0000 16'b0000000000010000 16'b0000000000010000
RXCDR_CFG3_GEN4 16'h0024 16'h0000 16'b0000000000010010 16'b0000000000010010
RXCDR_CFG4 16'h0000 16'h0000 16'b0000000000000000 16'h5CF6 16'h5AD6 16'b0101110011110110 16'b0101110011110110
RXCDR_CFG4_GEN3 16'h0000 16'h0000 16'b0000000000000000 16'h5CF6 16'h0000 16'b0101110011110110 16'b0101110011110110
RXCDR_CFG5 16'h0000 16'h0000 16'b0000000000000000 16'hB46B 16'hB46B 16'b1011010001101011 16'b1011010001101011
RXCDR_CFG5_GEN3 16'h0000 16'h0000 16'b0000000000000000 16'h146B 16'h0000 16'b0001010001101011 16'b0001010001101011
RXCDR_FR_RESET_ON_EIDLE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RXCDR_HOLD_DURING_EIDLE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RXCDR_LOCK_CFG0 16'h5080 16'h5080 16'b0100010010000000 16'h0040 16'h0000 16'b0010001000000001 16'b0010001000000001
RXCDR_LOCK_CFG1 16'h07E0 16'h07E0 16'b0101111111111111 16'h8000 16'h0000 16'b1001111111111111 16'b1001111111111111
RXCDR_LOCK_CFG2 16'h7C42 16'h7C42 16'b0111011111000011 16'h0000 16'h0000 16'b0111011111000011 16'b0111011111000011
RXCDR_LOCK_CFG3 16'h0000 16'h0000 16'b0000000000000001 16'b0000000000000001
RXCDR_LOCK_CFG4 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXCDR_PH_RESET_ON_EIDLE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RXCFOK_CFG0 16'h4000 16'h4000 16'b0100000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXCFOK_CFG1 16'h0060 16'h0060 16'b0000000001100101 16'h0002 16'h0002 16'b1000000000010101 16'b1000000000010101
RXCFOK_CFG2 16'h000E 16'h000E 16'b0000000000101110 16'h002D 16'h002D 16'b0000001010101110 16'b0000001010101110
RXCKCAL1_IQ_LOOP_RST_CFG 16'h0000 16'h0000 16'b0000000000000100 16'b0000000000000100
RXCKCAL1_I_LOOP_RST_CFG 16'h0000 16'h0000 16'b0000000000000100 16'b0000000000000100
RXCKCAL1_Q_LOOP_RST_CFG 16'h0000 16'h0000 16'b0000000000000100 16'b0000000000000100
RXCKCAL2_DX_LOOP_RST_CFG 16'h0000 16'h0000 16'b0000000000000100 16'b0000000000000100
RXCKCAL2_D_LOOP_RST_CFG 16'h0000 16'h0000 16'b0000000000000100 16'b0000000000000100
RXCKCAL2_S_LOOP_RST_CFG 16'h0000 16'h0000 16'b0000000000000100 16'b0000000000000100
RXCKCAL2_X_LOOP_RST_CFG 16'h0000 16'h0000 16'b0000000000000100 16'b0000000000000100
RXDFELPMRESET_TIME 7'b0001111 7'b0001111 7'b0001111 7'b0001111 7'b0001111 7'b0001111 7'b0001111
RXDFELPM_KL_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFELPM_KL_CFG1 16'h0032 16'h0032 16'b0000000000000010 16'h0022 16'h0022 16'b1010000011100010 16'b1010000011100010
RXDFELPM_KL_CFG2 16'h0000 16'h0000 16'b0000000000000000 16'h0100 16'h0100 16'b0000000100000000 16'b0000000100000000
RXDFE_CFG0 16'h0A00 16'h0A00 16'b0000101000000000 16'h4000 16'h4000 16'b0000101000000000 16'b0000101000000000
RXDFE_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_GC_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_GC_CFG1 16'h7840 16'h7840 16'b0111100001110000 16'h0000 16'h0000 16'b1000000000000000 16'b1000000000000000
RXDFE_GC_CFG2 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b1111111111100000 16'b1111111111100000
RXDFE_H2_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_H2_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b0000000000000010 16'b0000000000000010
RXDFE_H3_CFG0 16'h4000 16'h4000 16'b0100000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_H3_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_H4_CFG0 16'h2000 16'h2000 16'b0010000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_H4_CFG1 16'h0003 16'h0003 16'b0000000000000011 16'h0003 16'h0003 16'b1000000000000010 16'b1000000000000010
RXDFE_H5_CFG0 16'h2000 16'h2000 16'b0010000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_H5_CFG1 16'h0003 16'h0003 16'b0000000000000011 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_H6_CFG0 16'h2000 16'h2000 16'b0010000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_H6_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_H7_CFG0 16'h2000 16'h2000 16'b0010000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_H7_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_H8_CFG0 16'h2000 16'h2000 16'b0010000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_H8_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_H9_CFG0 16'h2000 16'h2000 16'b0010000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_H9_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_HA_CFG0 16'h2000 16'h2000 16'b0010000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_HA_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_HB_CFG0 16'h2000 16'h2000 16'b0010000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_HB_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_HC_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_HC_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_HD_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_HD_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_HE_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_HE_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_HF_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_HF_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_KH_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_KH_CFG1 16'h0000 16'h0000 16'b1000000000000000 16'b1000000000000000
RXDFE_KH_CFG2 16'h0000 16'h0000 16'b0010011000010011 16'b0010011000010011
RXDFE_KH_CFG3 16'h0000 16'h0000 16'b0100000100011100 16'b0100000100011100
RXDFE_OS_CFG0 16'h8000 16'h8000 16'b1000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_OS_CFG1 16'h0000 16'h0000 16'b0000000000000000 16'h0002 16'h0002 16'b1000000000000010 16'b1000000000000010
RXDFE_PWR_SAVING 1'b0 1'b0 1'b1 1'b1
RXDFE_UT_CFG0 16'h8000 16'h8000 16'b1000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_UT_CFG1 16'h0003 16'h0003 16'b0000000000000011 16'h0002 16'h0002 16'b0000000000000011 16'b0000000000000011
RXDFE_UT_CFG2 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_VP_CFG0 16'hAA00 16'hAA00 16'b1010101000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXDFE_VP_CFG1 16'h0033 16'h0033 16'b0000000000110011 16'h0022 16'h0022 16'b1000000000110011 16'b1000000000110011
RXDLY_CFG 16'h001F 16'h001F 16'b0000000000011111 16'h0010 16'h0010 16'b0000000000010000 16'b0000000000010000
RXDLY_LCFG 16'h0030 16'h0030 16'b0000000000110000 16'h0030 16'h0030 16'b0000000000110000 16'b0000000000110000
RXELECIDLE_CFG "Sigcfg_4" "Sigcfg_4" "Sigcfg_4" "SIGCFG_4" "SIGCFG_4" "SIGCFG_4" "SIGCFG_4"
RXGBOX_FIFO_INIT_RD_ADDR 4 4 4 4 4 4 4
RXGEARBOX_EN "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
RXISCANRESET_TIME 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001
RXLPM_CFG 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXLPM_GC_CFG 16'h0000 16'h0000 16'b0001000000000000 16'h1000 16'h1000 16'b1000000000000000 16'b1000000000000000
RXLPM_KH_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXLPM_KH_CFG1 16'h0002 16'h0002 16'b0000000000000010 16'h0002 16'h0002 16'b0000000000000010 16'b0000000000000010
RXLPM_OS_CFG0 16'h8000 16'h8000 16'b1000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXLPM_OS_CFG1 16'h0002 16'h0002 16'b0000000000000010 16'h0000 16'h0000 16'b1000000000000010 16'b1000000000000010
RXOOB_CFG 9'b000000110 9'b000000110 9'b000000110 9'b000110000 9'b000110000 9'b000000110 9'b000000110
RXOOB_CLK_CFG "PMA" "PMA" "PMA" "PMA" "PMA" "PMA" "PMA"
RXOSCALRESET_TIME 5'b00011 5'b00011 5'b00011 5'b00011 5'b00011 5'b00011 5'b00011
RXOUT_DIV 4 4 1 4 4 1 1
RXPCSRESET_TIME 5'b00001 5'b00001 5'b00011 5'b00001 5'b00001 5'b00011 5'b00011
RXPHBEACON_CFG 16'h0000 16'h0000 16'b0000000000000000 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RXPHDLY_CFG 16'h2020 16'h2020 16'b0010000000100000 16'h2020 16'h2020 16'b0010000001110000 16'b0010000001110000
RXPHSAMP_CFG 16'h2100 16'h2100 16'b0010000100000000 16'h2100 16'h2100 16'b0010000100000000 16'b0010000100000000
RXPHSLIP_CFG 16'h6622 16'h6622 16'b0110011000100010 16'h9933 16'h9933 16'b1001100100110011 16'b1001100100110011
RXPH_MONITOR_SEL 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000
RXPI_AUTO_BW_SEL_BYPASS 1'b0 1'b0 1'b0 1'b0
RXPI_CFG0 2'b00 2'b00 2'b00 16'h0002 16'h0002 16'b0000000000000010 16'b0000000000000010
RXPI_CFG1 2'b00 2'b00 2'b00 16'b0000000000000000 16'b0000000000000000 16'b0000000000010101 16'b0000000000010101
RXPI_CFG2 2'b00 2'b00 2'b00
RXPI_CFG3 2'b00 2'b00 2'b00
RXPI_CFG4 1'b0 1'b0 1'b0
RXPI_CFG5 1'b1 1'b1 1'b1
RXPI_CFG6 3'b000 3'b000 3'b000
RXPI_LPM 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RXPI_SEL_LC 2'b00 2'b00 2'b00 2'b00
RXPI_STARTCODE 2'b00 2'b00 2'b00 2'b00
RXPI_VREFSEL 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RXPMACLK_SEL "DATA" "DATA" "DATA" "DATA" "DATA" "DATA" "DATA"
RXPMARESET_TIME 5'b00001 5'b00001 5'b00011 5'b00001 5'b00001 5'b00011 5'b00011
RXPRBS_ERR_LOOPBACK 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RXPRBS_LINKACQ_CNT 15 15 15 15 15 15 15
RXREFCLKDIV2_SEL 1'b0 1'b0 1'b0 1'b0
RXSLIDE_AUTO_WAIT 7 7 7 7 7 7 7
RXSLIDE_MODE "OFF" "OFF" "OFF" "OFF" "OFF" "OFF" "OFF"
RXSYNC_MULTILANE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RXSYNC_OVRD 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RXSYNC_SKIP_DA 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_AFE_CM_EN 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_BIAS_CFG0 16'h0AD4 16'h0AD4 16'b0000101010110100 16'h12B0 16'h12B0 16'b0001010101010100 16'b0001010101010100
RX_BUFFER_CFG 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000
RX_CAPFF_SARC_ENB 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_CLK25_DIV 8 8 3 8 8 3 3
RX_CLKMUX_EN 1'b1 1'b1 1'b1 1'b1 1'b1 1'b1 1'b1
RX_CLK_SLIP_OVRD 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000
RX_CM_BUF_CFG 4'b1010 4'b1010 4'b1010 4'b1010 4'b1010 4'b1010 4'b1010
RX_CM_BUF_PD 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_CM_SEL 2'b11 2'b11 2'b11 3 3 3 3
RX_CM_TRIM 4'b0100 4'b0100 4'b1010 12 12 10 10
RX_CTLE3_LPF 8'b00000000 8'b00000000 8'b00000001 8'b00000000 8'b00000000 8'b11111111 8'b11111111
RX_DATA_WIDTH 20 20 32 20 20 32 32
RX_DDI_SEL 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000
RX_DEFER_RESET_BUF_EN "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
RX_DEGEN_CTRL 3'b011 3'b011 3'b011 3'b011
RX_DFELPM_CFG0 4'b0110 4'b0110 4'b0110 0 0 6 6
RX_DFELPM_CFG1 1'b0 1'b0 1'b1 1'b1 1'b1 1'b1 1'b1
RX_DFELPM_KLKH_AGC_STUP_EN 1'b1 1'b1 1'b1 1'b1 1'b1 1'b1 1'b1
RX_DFE_AGC_CFG0 2'b00 2'b00 2'b10 2'b00 2'b00 2'b10 2'b10
RX_DFE_AGC_CFG1 3'b100 3'b100 3'b100 4 4 4 4
RX_DFE_KL_LPM_KH_CFG0 2'b01 2'b01 2'b01 1 1 1 1
RX_DFE_KL_LPM_KH_CFG1 3'b010 3'b010 3'b100 4 4 4 4
RX_DFE_KL_LPM_KL_CFG0 2'b01 2'b01 2'b01 2'b01 2'b01 2'b01 2'b01
RX_DFE_KL_LPM_KL_CFG1 3'b010 3'b010 3'b100 4 4 4 4
RX_DFE_LPM_HOLD_DURING_EIDLE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_DISPERR_SEQ_MATCH "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
RX_DIV2_MODE_B 1'b0 1'b0 1'b0 1'b0
RX_DIVRESET_TIME 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001
RX_EN_CTLE_RCAL_B 1'b0 1'b0 1'b0 1'b0
RX_EN_HI_LR 1'b0 1'b0 1'b1 1'b1 1'b1 1'b1 1'b1
RX_EXT_RL_CTRL 9'b000000000 9'b000000000 9'b000000000 9'b000000000
RX_EYESCAN_VS_CODE 7'b0000000 7'b0000000 7'b0000000 7'b0000000 7'b0000000 7'b0000000 7'b0000000
RX_EYESCAN_VS_NEG_DIR 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_EYESCAN_VS_RANGE 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00
RX_EYESCAN_VS_UT_SIGN 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_FABINT_USRCLK_FLOP 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_INT_DATAWIDTH 1 1 1 1 1 1 1
RX_PMA_POWER_SAVE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_PMA_RSV0 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
RX_PROGDIV_CFG 0 0 0 0 0 0 0
RX_PROGDIV_RATE 16'h0001 16'h0001 16'b0000000000000001 16'b0000000000000001
RX_RESLOAD_CTRL 4'b0000 4'b0000 4'b0000 4'b0000
RX_RESLOAD_OVRD 1'b0 1'b0 1'b0 1'b0
RX_SAMPLE_PERIOD 3'b101 3'b101 3'b111 3'b101 3'b101 3'b111 3'b111
RX_SIG_VALID_DLY 11 11 11 11 11 11 11
RX_SUM_DFETAPREP_EN 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_SUM_IREF_TUNE 4'b0000 4'b0000 4'b0000 4'b1001 4'b1001 4'b1001 4'b1001
RX_SUM_RESLOAD_CTRL 4'b0000 4'b0000 4'b0011 4'b0011
RX_SUM_RES_CTRL 2'b00 2'b00 2'b00
RX_SUM_VCMTUNE 4'b0000 4'b0000 4'b0000 4'b1010 4'b1010 4'b1010 4'b1010
RX_SUM_VCM_OVWR 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
RX_SUM_VREF_TUNE 3'b000 3'b000 3'b000 3'b100 3'b100 3'b100 3'b100
RX_TUNE_AFE_OS 2'b00 2'b00 2'b10 2'b00 2'b00 2'b00 2'b00
RX_VREG_CTRL 3'b101 3'b101 3'b101 3'b101
RX_VREG_PDB 1'b1 1'b1 1'b1 1'b1
RX_WIDEMODE_CDR 1'b0 1'b0 1'b1 2'b01 2'b01 2'b01 2'b01
RX_WIDEMODE_CDR_GEN3 2'b01 2'b01 2'b00 2'b00
RX_WIDEMODE_CDR_GEN4 2'b01 2'b01 2'b01 2'b01
RX_XCLK_SEL "RXDES" "RXDES" "RXDES" "RXDES" "RXDES" "RXDES" "RXDES"
RX_XMODE_SEL 1'b0 1'b0 1'b0 1'b0
SAMPLE_CLK_PHASE 1'b0 1'b0 1'b0 1'b0
SAS_12G_MODE 1'b0 1'b0 1'b0 1'b0
SAS_MAX_COM 64 64 64
SAS_MIN_COM 36 36 36
SATA_BURST_SEQ_LEN 4'b1111 4'b1111 4'b1110 4'b1111 4'b1111 4'b1111 4'b1111
SATA_CPLL_CFG "VCO_3000MHZ" "VCO_3000MHZ" "VCO_3000MHZ" "VCO_3000MHZ" "VCO_3000MHZ" "VCO_3000MHZ" "VCO_3000MHZ"
SATA_MAX_BURST 8 8 8
SATA_MAX_INIT 21 21 21
SATA_MAX_WAKE 7 7 7
SATA_MIN_BURST 4 4 4
SATA_MIN_INIT 12 12 12
SATA_MIN_WAKE 4 4 4
SHOW_REALIGN_COMMA "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
SIM_DEVICE "ULTRASCALE_PLUS" "ULTRASCALE_PLUS" "ULTRASCALE_PLUS" "ULTRASCALE_PLUS"
SIM_MODE "FAST" "FAST" "FAST" "FAST" "FAST"
SIM_RECEIVER_DETECT_PASS "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
SIM_RESET_SPEEDUP "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
SIM_TX_EIDLE_DRIVE_LEVEL 1'b0 1'b0 1'b0 "Z" "Z" "Z" "Z"
SIM_VERSION 2 2 2
SRSTMODE 1'b0 1'b0 1'b0 1'b0
TAPDLY_SET_TX 2'h0 2'h0 2'b00 2'h0 2'h0 2'b00 2'b00
TEMPERATURE_PAR 4'b0010 4'b0010 4'b0010 4'b0010
TEMPERATUR_PAR 4'b0010 4'b0010 4'b0010
TERM_RCAL_CFG 15'b100001000010000 15'b100001000010000 15'b100001000010000 15'b100001000010000 15'b100001000010000 15'b100001000010001 15'b100001000010001
TERM_RCAL_OVRD 3'b000 3'b000 3'b000 3'b000 3'b000 3'b000 3'b000
TRANS_TIME_RATE 8'h0E 8'h0E 8'b00001110 8'h0E 8'h0E 8'b00001110 8'b00001110
TST_RSV0 8'h00 8'h00 8'b00000000 8'h00 8'h00 8'b00000000 8'b00000000
TST_RSV1 8'h00 8'h00 8'b00000000 8'h00 8'h00 8'b00000000 8'b00000000
TXBUF_EN "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE" "TRUE"
TXBUF_RESET_ON_RATE_CHANGE "FALSE" "FALSE" "TRUE" "FALSE" "FALSE" "TRUE" "TRUE"
TXDLY_CFG 16'h001F 16'h001F 16'b0000000000001001 16'h0010 16'h0010 16'b1000000000010000 16'b1000000000010000
TXDLY_LCFG 16'h0030 16'h0030 16'b0000000001010000 16'h0030 16'h0030 16'b0000000000110000 16'b0000000000110000
TXDRVBIAS_N 4'b1010 4'b1010 4'b1010 4'b1010 4'b1010 4'b1010 4'b1010
TXDRVBIAS_P 4'b1100 4'b1100 4'b1010
TXFIFO_ADDR_CFG "LOW" "LOW" "LOW" "LOW" "LOW" "LOW" "LOW"
TXGBOX_FIFO_INIT_RD_ADDR 4 4 4 4 4 4 4
TXGEARBOX_EN "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
TXOUT_DIV 4 4 1 4 4 1 1
TXPCSRESET_TIME 5'b00001 5'b00001 5'b00011 5'b00001 5'b00001 5'b00011 5'b00011
TXPHDLY_CFG0 16'h2020 16'h2020 16'b0010000000100000 16'h6020 16'h6020 16'b0110000001110000 16'b0110000001110000
TXPHDLY_CFG1 16'h0001 16'h0001 16'b0000000001110101 16'h0002 16'h0002 16'b0000000000001110 16'b0000000000001110
TXPH_CFG 16'h0980 16'h0980 16'b0000100110000000 16'h0123 16'h8123 16'b0000001100100011 16'b0000001100100011
TXPH_CFG2 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
TXPH_MONITOR_SEL 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000 5'b00000
TXPI_CFG 16'h0000 16'h0000 16'b0000000001010100 16'b0000000001010100
TXPI_CFG0 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00
TXPI_CFG1 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00
TXPI_CFG2 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00 2'b00
TXPI_CFG3 1'b0 1'b0 1'b1 1'b0 1'b0 1'b0 1'b0
TXPI_CFG4 1'b1 1'b1 1'b1 1'b1 1'b1 1'b0 1'b0
TXPI_CFG5 3'b000 3'b000 3'b000 3'b000 3'b000 3'b000 3'b000
TXPI_GRAY_SEL 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TXPI_INVSTROBE_SEL 1'b0 1'b0 1'b1 1'b0 1'b0 1'b0 1'b0
TXPI_LPM 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TXPI_PPM 1'b0 1'b0 1'b0 1'b0
TXPI_PPMCLK_SEL "TXUSRCLK2" "TXUSRCLK2" "TXUSRCLK2" "TXUSRCLK2" "TXUSRCLK2" "TXUSRCLK2" "TXUSRCLK2"
TXPI_PPM_CFG 8'b00000000 8'b00000000 8'b00000000 8'b00000000 8'b00000000 8'b00000000 8'b00000000
TXPI_SYNFREQ_PPM 3'b000 3'b000 3'b001 3'b000 3'b000 3'b001 3'b001
TXPI_VREFSEL 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TXPMARESET_TIME 5'b00001 5'b00001 5'b00011 5'b00001 5'b00001 5'b00011 5'b00011
TXREFCLKDIV2_SEL 1'b0 1'b0 1'b0 1'b0
TXSYNC_MULTILANE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TXSYNC_OVRD 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TXSYNC_SKIP_DA 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TX_CLK25_DIV 8 8 3 8 8 3 3
TX_CLKMUX_EN 1'b1 1'b1 1'b1 1'b1 1'b1 1'b1 1'b1
TX_DATA_WIDTH 20 20 32 20 20 32 32
TX_DCC_LOOP_RST_CFG 16'h0000 16'h0000 16'b0000000000000100 16'b0000000000000100
TX_DCD_CFG 6'b000010 6'b000010 6'b000010
TX_DCD_EN 1'b0 1'b0 1'b0
TX_DEEMPH0 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000
TX_DEEMPH1 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000 6'b000000
TX_DEEMPH2 6'b000000 6'b000000 6'b000000 6'b000000
TX_DEEMPH3 6'b000000 6'b000000 6'b000000 6'b000000
TX_DIVRESET_TIME 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001 5'b00001
TX_DRIVE_MODE "DIRECT" "DIRECT" "DIRECT" "DIRECT" "DIRECT" "DIRECT" "DIRECT"
TX_DRVMUX_CTRL 2 2 2 2
TX_EIDLE_ASSERT_DELAY 3'b110 3'b110 3'b100 3'b110 3'b110 3'b100 3'b100
TX_EIDLE_DEASSERT_DELAY 3'b100 3'b100 3'b011 3'b100 3'b100 3'b011 3'b011
TX_EML_PHI_TUNE 1'b0 1'b0 1'b0
TX_FABINT_USRCLK_FLOP 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TX_FIFO_BYP_EN 1'b0 1'b0 1'b0 1'b0
TX_IDLE_DATA_ZERO 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TX_INT_DATAWIDTH 1 1 1 1 1 1 1
TX_LOOPBACK_DRIVE_HIZ "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE" "FALSE"
TX_MAINCURSOR_SEL 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TX_MARGIN_FULL_0 7'b1001110 7'b1001110 7'b1001111 7'b1001110 7'b1001110 7'b1011111 7'b1011111
TX_MARGIN_FULL_1 7'b1001001 7'b1001001 7'b1001110 7'b1001001 7'b1001001 7'b1011110 7'b1011110
TX_MARGIN_FULL_2 7'b1000101 7'b1000101 7'b1001100 7'b1000101 7'b1000101 7'b1011100 7'b1011100
TX_MARGIN_FULL_3 7'b1000010 7'b1000010 7'b1001010 7'b1000010 7'b1000010 7'b1011010 7'b1011010
TX_MARGIN_FULL_4 7'b1000000 7'b1000000 7'b1001000 7'b1000000 7'b1000000 7'b1011000 7'b1011000
TX_MARGIN_LOW_0 7'b1000110 7'b1000110 7'b1000110 7'b1000110 7'b1000110 7'b1000110 7'b1000110
TX_MARGIN_LOW_1 7'b1000100 7'b1000100 7'b1000101 7'b1000100 7'b1000100 7'b1000101 7'b1000101
TX_MARGIN_LOW_2 7'b1000010 7'b1000010 7'b1000011 7'b1000010 7'b1000010 7'b1000011 7'b1000011
TX_MARGIN_LOW_3 7'b1000000 7'b1000000 7'b1000010 7'b1000000 7'b1000000 7'b1000010 7'b1000010
TX_MARGIN_LOW_4 7'b1000000 7'b1000000 7'b1000000 7'b1000000 7'b1000000 7'b1000000 7'b1000000
TX_MODE_SEL 3'b000 3'b000 3'b000
TX_PHICAL_CFG0 16'h0000 16'h0000 16'b0000000000000000 16'b0000000000000000
TX_PHICAL_CFG1 16'h003F 16'h7E00 16'b0111111000000000 16'b0111111000000000
TX_PHICAL_CFG2 16'h0000 16'h0000 16'b0000001000000001 16'b0000001000000001
TX_PI_BIASSET 0 0 1 1
TX_PI_IBIAS_MID 2'b00 2'b00 2'b00 2'b00
TX_PMADATA_OPT 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TX_PMA_POWER_SAVE 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TX_PMA_RSV0 16'h0008 16'h0000 16'b0000000000001000 16'b0000000000001000
TX_PREDRV_CTRL 2 2 2 2
TX_PROGCLK_SEL "POSTPI" "POSTPI" "PREPI" "POSTPI" "POSTPI" "PREPI" "PREPI"
TX_PROGDIV_CFG 0 0 0 0 0 0 0
TX_PROGDIV_RATE 16'h0001 16'h0001 16'b0000000000000001 16'b0000000000000001
TX_QPI_STATUS_EN 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TX_RXDETECT_CFG 14'h0032 14'h0032 14'b00000000110010 14'h0032 14'h0032 14'b00000000110010 14'b00000000110010
TX_RXDETECT_REF 3'b100 3'b100 3'b100 3 3 4 4
TX_SAMPLE_PERIOD 3'b101 3'b101 3'b111 3'b101 3'b101 3'b111 3'b111
TX_SARC_LPBK_ENB 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TX_SW_MEAS 2'b00 2'b00 2'b00 2'b00
TX_VREG_CTRL 3'b000 3'b000 3'b000 3'b000
TX_VREG_PDB 1'b0 1'b0 1'b0 1'b0
TX_VREG_VREFSEL 2'b00 2'b00 2'b00 2'b00
TX_XCLK_SEL "TXOUT" "TXOUT" "TXOUT" "TXOUT" "TXOUT" "TXOUT" "TXOUT"
USB_BOTH_BURST_IDLE 1'b0 1'b0 1'b0 1'b0
USB_BURSTMAX_U3WAKE 7'b1111111 7'b1111111 7'b1111111 7'b1111111
USB_BURSTMIN_U3WAKE 7'b1100011 7'b1100011 7'b1100011 7'b1100011
USB_CLK_COR_EQ_EN 1'b0 1'b0 1'b0 1'b0
USB_EXT_CNTL 1'b1 1'b1 1'b1 1'b1
USB_IDLEMAX_POLLING 10'b1010111011 10'b1010111011 10'b1010111011 10'b1010111011
USB_IDLEMIN_POLLING 10'b0100101011 10'b0100101011 10'b0100101011 10'b0100101011
USB_LFPSPING_BURST 9'b000000101 9'b000000101 9'b000000101 9'b000000101
USB_LFPSPOLLING_BURST 9'b000110001 9'b000110001 9'b000110001 9'b000110001
USB_LFPSPOLLING_IDLE_MS 9'b000000100 9'b000000100 9'b000000100 9'b000000100
USB_LFPSU1EXIT_BURST 9'b000011101 9'b000011101 9'b000011101 9'b000011101
USB_LFPSU2LPEXIT_BURST_MS 9'b001100011 9'b001100011 9'b001100011 9'b001100011
USB_LFPSU3WAKE_BURST_MS 9'b111110011 9'b111110011 9'b111110011 9'b111110011
USB_LFPS_TPERIOD 4'b0011 4'b0011 4'b0011 4'b0011
USB_LFPS_TPERIOD_ACCURATE 1'b1 1'b1 1'b1 1'b1
USB_MODE 1'b0 1'b0 1'b0 1'b0
USB_PCIE_ERR_REP_DIS 1'b0 1'b0 1'b0 1'b0
USB_PING_SATA_MAX_INIT 21 21 21 21
USB_PING_SATA_MIN_INIT 12 12 12 12
USB_POLL_SATA_MAX_BURST 8 8 8 8
USB_POLL_SATA_MIN_BURST 4 4 4 4
USB_RAW_ELEC 1'b0 1'b0 1'b0 1'b0
USB_RXIDLE_P0_CTRL 1'b1 1'b1 1'b1 1'b1
USB_TXIDLE_TUNE_ENABLE 1'b1 1'b1 1'b1 1'b1
USB_U1_SATA_MAX_WAKE 7 7 7 7
USB_U1_SATA_MIN_WAKE 4 4 4 4
USB_U2_SAS_MAX_COM 64 64 64 64
USB_U2_SAS_MIN_COM 36 36 36 36
USE_PCS_CLK_PHASE_SEL 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
WB_MODE 2'b00 2'b00 2'b00
Y_ALL_MODE 1'b0 1'b0 1'b0 1'b0