/******************************************************************************
 * Copyright (c) ETSI 2017.
 *
 * This file is subject to copyrights owned by ETSI. Non-exclusive permission
 * is hereby granted, free of charge, to copy, reproduce and amend this file
 * under the following conditions: It is provided "as is", without warranty of any
 * kind, expressed or implied.
 * 
 * ETSI shall never be liable for any claim, damages, or other liability arising
 * from its use or inability of use.This permission does not apply to any documentation
 * associated with this file for which ETSI keeps all rights reserved. The present
 * copyright notice shall be included in all copies of whole or part of this
 * file and shall not imply any sub-license right.
 *
 * Modified by: Adrien Kirjak
 *
 * @version 0.0.1
 * @purpose 1:20.4, Validate that interleave statements are properly handled.
 * @verdict pass accept, noexecution
 *****************************************************************/
module Syn_2004_InterleaveStatement_001 {
    type port MyMessagePortType message {
        inout MyMessageType;
    } with {extension "internal"}

    type component GeneralComp {
        port MyMessagePortType pt_myPort1, pt_myPort2;
    }

    type record MyMessageType {
        integer field1,
        charstring field2,
        boolean field3
    }

    testcase TC_Syn_2004_InterleaveStatement_001() runs on GeneralComp {

        template MyMessageType MySig1 := {2, "abcxyz", true}
        template MyMessageType MySig2 := MySig1;
        template MyMessageType MySig3 := MySig1;
        template MyMessageType MySig4 := MySig1;
        template MyMessageType MySig5 := MySig1;
        template MyMessageType MySig6 := MySig1;

		connect(self:pt_myPort1, self:pt_myPort2);

        pt_myPort1
        .send(MyMessageType: 
              {
                  2,
                  "abcxyz",
                  true
              });

        interleave { // order of messages
            [] pt_myPort1.receive(MySig1) { //3.
                pt_myPort1.send(MySig2); //4.
                pt_myPort1.receive(MySig3); //6.
				setverdict(pass);
            }
            [] pt_myPort2.receive(MySig4) { // 1.
                pt_myPort2.send(MySig5); //2.
                pt_myPort2.receive(MySig6); //5.
				pt_myPort2.send(MySig1); //7.
            }
        }
    }
    control {
        execute(TC_Syn_2004_InterleaveStatement_001());
    }
}
