/******************************************************************************
 * Copyright (c) ETSI 2017.
 *
 * This file is subject to copyrights owned by ETSI. Non-exclusive permission
 * is hereby granted, free of charge, to copy, reproduce and amend this file
 * under the following conditions: It is provided "as is", without warranty of any
 * kind, expressed or implied.
 * 
 * ETSI shall never be liable for any claim, damages, or other liability arising
 * from its use or inability of use.This permission does not apply to any documentation
 * associated with this file for which ETSI keeps all rights reserved. The present
 * copyright notice shall be included in all copies of whole or part of this
 * file and shall not imply any sub-license right.
 *
 * Modified by: Adrien Kirjak
 *
 ** @version  0.0.1
 ** @purpose  1:21.1, Verify that map operation fails if both operands are component ports
 ** @verdict  pass reject
 ***************************************************/

// The following requirements are tested:
// When connecting a test component to a test system interface the map operation shall be used.

module NegSem_2101_TopLevel_002 { 
	type port P message {
		inout integer;
	} with {extension "internal"}
	
	type component GeneralComp {
		port P p;
	}

	testcase TC_NegSem_210101_TopLevel_002() runs on GeneralComp system GeneralComp {
		var GeneralComp v_ptc := GeneralComp.create;
		map(self:p, v_ptc:p); // error expected
		setverdict(pass);
	}
	
	control{
	    execute(TC_NegSem_210101_TopLevel_002());
	}
}
