/******************************************************************************
 * Copyright (c) ETSI 2017.
 *
 * This file is subject to copyrights owned by ETSI. Non-exclusive permission
 * is hereby granted, free of charge, to copy, reproduce and amend this file
 * under the following conditions: It is provided "as is", without warranty of any
 * kind, expressed or implied.
 * 
 * ETSI shall never be liable for any claim, damages, or other liability arising
 * from its use or inability of use.This permission does not apply to any documentation
 * associated with this file for which ETSI keeps all rights reserved. The present
 * copyright notice shall be included in all copies of whole or part of this
 * file and shall not imply any sub-license right.
 *
 * Modified by: Adrien Kirjak
 *
 ** @version  0.0.1
 ** @purpose  1:23, Ensure timer start  syntax
 ** @verdict  pass reject
 ***************************************************/
// #reqname  /Requirements/23 Timer operations/23.2 The start timer operation/Start timer syntax


module NegSyn_2302_timer_start_008 {
    type component TComp{
        
        timer t_timer := 1.0; 
    }

    testcase TC_NegSyn_2302_timer_start_008() runs on TComp{
        
        t_timer start;
        
    }

    control{
        
            execute(TC_NegSyn_2302_timer_start_008())
       
        
    }
}
